1. Field of the Invention
The present invention relates to a memory device and a memory device read method that cope with variation in timing of a read operation.
2. Description of the Related Art
Firstly, a conventional memory device will be described. Here, a RAM is taken as an example of the memory device. FIG. 5 is a block diagram showing a configuration example of a conventional RAM (Random Access Memory). The RAM includes latches 1, 2, and 3, a memory cell 4, a delay circuit 15, a sense enable signal generation section 6, and a sense amplifier 7.
The latch 1 latches an address signal input from an external device and outputs it to the memory cell 4 and sense enable signal generation section 6. The latch 2 latches a written enable signal input from an external device and outputs it to the memory cell 4 and sense enable signal generation section 6. The latch 3 latches a write data signal input from an external device and outputs it to the memory cell 4. The delay circuit 15 delays a CLK (clock) signal according to a value represented by a CT (clock tune) signal input from an external device and outputs the CLK signal to the sense enable signal generation section 6 as a CLK_delay signal. The sense enable signal generation section 6 generates a sense enable signal using outputs of the latches 1 and 2 and CLK_delay signal and outputs it to the sense amplifier 7. The timing of the sense enable signal is synchronous with the rise edge of the CLK_delay signal.
A description will next be given of a read operation. FIGS. 6A and 6B are timing charts of a read operation in the conventional RAM. FIG. 6A is a timing chart of a read operation with a high frequency CLK signal; and FIG. 6B is a timing chart of a read operation with a low frequency CLK signal. The memory cell 4 outputs a result obtained by reading out the data designated by the address signal to the sense amplifier 7 as a bit signal and bit_b signal. The sense amplifier 7 amplifies the difference of the bit signal and bit_b signal while the sense enable signal is ON and outputs the obtained signal to an external device as a read data signal. As shown in FIG. 6A, the delay circuit 15 provides a delay amount Ta to the CLK signal to generate a CLK_delay signal in order to align the timing with the bit signal and bit_b signal, and a sense enable signal is generated in synchronization with the rise edge of the CLK_delay signal.
Therefore, in RAM design, it is important for the sense amplifier 7 to amplify the potential change of the bit signal and bit_b signal read out from the memory cell 4 at high speed. That is, how the timing at which the sense enable signal is ON is allowed to coincide with the timing of the potential change of the bit signal and bit_b signal is important.
FIG. 7 is a table showing a setting example of the delay amount in the conventional delay circuit. In this example, a 3-bit CT signal consisting of CT[0], CT[1] and CT[2] is input to the delay circuit 15. The delay circuit 15 switches the number of internal delay elements in accordance with the numerical value represented by the CT signal to control the delay of the sense enable signal with respect to the rise edge of the CLK signal within a range of −20 ps to +120 ps.
While the time required from the activation of a word line of the RAM to the change in bit line potential varies depending on a process, it is possible to cope with variation in the process to some degree by controlling the timing of the sense enable signal using the CT from an external device.
As the conventional art related to the present invention, for example, Jpn. Pat. Appln. Laid-open Publication No. 2000-163966 (pages 3 to 8, FIG. 1) is known.
However, in the case where processes differ greatly or the RAM that has been operated with high frequency is operated with low frequency, the timing of sense enable signal greatly differs from that of the change in bit line potential. As shown in FIG. 6B, in the case where the RAM is operated with a low frequency CLK signal, the time required from the rise edge of the CLK signal to the timing of bit signal and bit_b signal becomes longer than in the case of FIG. 6A. In this case, the required time exceeds the delay amount Tb that the delay circuit 15 can provide to the CLK signal, with the result that the timing of sense enable signal cannot coincide with that of bit signal and bit_b signal.